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dvdp data processor ic KS1453 1 1 product overview introduction KS1453 is a data processing ic that can operate in 1x dvdp or 4x cd (audio/ vcd) mode. it receives the sliced output (efm signals) of the rf signal from the disc and carries out data demodulation and error correction. it includes a buffer control feature that allows the demodulated data to be continuously output in hand shake mode. features ? external plck input ? efm/efmplus demodulator ? sync protection/insertion ? circ/rs-pc error correction (4/16 erasure correction) ? cross/row deinterleave ? 4 - 16 mbits dram interface (external component for error correction/track buffering) ? descramble ? id error correction ? main data error detection (edc) ? error flag monitoring ? micom interface ? micom direct memory access feature (dvd/cd) ? dsi detection and dsi data output ? a/v decoder parallel interface ? built-in cd-da decoder ? sub-code data serial output ? spindle servo control signal generation ? dvd playback ? cd/vcd playback ? clv/cav feature ? cd/vcd repeat correcting feature ? technology - application mode: cd_player, cd_rom, video-cd, dvdp player 128-qfp
KS1453 dvdp data processor ic 2 block diagram figure 1. block diagram to av (13) sdata[0]_out/cdata sdata[1]_out/lrck sdata[2]_out/bclk sdata[3]_out/c2po sdata[4]_out/sqdt sdata[5]_out/wfsy sdata[6]_out/sos1 sdata[7]_bi/sqck datreq_in cstrobe_out dter_out datack_out tos_out 32bit sr frame sync det/prot/ins (17.57khz) vco timing generator vco timing generator frame sync det/prot/ins (7.35khz) 23bit sr m x'tal & timing gen cd clv/cav dvd clv/cav m rfck 17.58/7.35khz 7.35khz = 4.3218m/588 17.58khz = 26.16m/1488 16-8 demod (6, 4, 3) efmwr id ecc (208, 192, 17) (182, 172, 11) ecc (32, 28, 5) (28, 24, 5) circ efm demod subcode i/f descrambler edc (6, 4, 3) trans id ecc deinterleave & ram control micom i/f m m v-cd, cd-da cd-g dvdp, sq-vcd to dram (32) 256k * 16 dd[15:0]_bi dadr[8:0]_out zras_out zucas_out zlcas_out zoe[1:0]_out zwe[1:0]_out to micom (15) mdat[7:0]_bi, mrza_in, zcs_in, mwr_in, mrd_in, zirqzd_out, zwait_out, zrst_in to rf (8) pwmo[7:0]_out from servo (3) efmi_in plck_in fg_in x'tal (4) xti_in xto_out ck33mi_in ck33mo_out to servo (6) mon_out mdp_out mds_out fsw_out plllock_out serlock_out monitor (9) gfs_out, frsyz_out, tx_out, efmo_out, clvlo ck_out, wfck_out, rfck_out, ck16m_out, dem pha_out power (34) = vdd (11) + gnd (23) test pin (4) testo_in, test1_in, test2_in, test3_in ecsy 75hz 676.08hz 26.16hz wfck 17.58/7.35khz
dvdp data processor ic KS1453 3 pin configuration figure 2. pin configuration KS1453 wfck_out efmo_out test2_in test1_in test0_in dvdd ck33mo_out ck33mi_in dvss gfs_out tx_out frsyz_out dvss dvss dvss dvss dvdd dvdd dvss dvss dvss pwmo0_out pwmo1_out pwmo2_out pwmo3_out dvdd pwmo4_out pwmo5_out pwmo6_out pwmo7_out dvss dter_out datreq_in cstrobe_out dvss sdata7_bi sdata6_out sdata5_out 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 83 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 27 28 29 30 31 32 33 34 35 36 37 38 dvss zcs_in mrza_in dvss mdat7_bi mdat6_bi mdat5_bi mdat4_bi mdat3_bi mdat2_bi mdat1_bi mdat0_bi dvdd xti_in xto_out dvss dd15_bi dd0_bi dd14_bi dd1_bi dvss dd13_bi dd2_bi dd12_bi dd3_bi dvdd dd11_bi dd4_bi dd10_bi dd5_bi dvss dd9_bi dd6_bi dd8_bi dd7_bi dvss zlcas_out zucas_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 119 120 121 123 122 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 44 45 43 42 41 40 39 rfck_out plck_in dvss plllock_out clvlock_out serlock_lock mdp_out mds_out dvss dvss mon_out fg_in fsw_out efmi_in dvdd dvdd dvdd ck16m_out dempha_out test3_in dvss zrst_in zwait_out zirqzd_out mrd_in mwr_in 118 sdata4_out sdata3_out sdata2_out sdata1_out sdata0_out dvdd datack_out tos_out dvss dvss dadr3_out dadr4_out dadr2_out dadr5_out dadr1_out dadr6_out dadr0_out dvss dadr7_out dadr8_out zras_out zoe0_out dvdd zoe1_out zwe0_out zwe1_out
KS1453 dvdp data processor ic 4 pin description table 1. pin description no pin name description i/o note 1 dvss digital gnd (0v) 2 zcs_in chip select (active low), pull_up pin i micom 3 mrza_in micom register select, pull_up pin (l ? register, h ? data) i micom 4 dvss digital gnd (0v) 5 mdat7_bi micom data bus b micom 6 mdat6_bi micom data bus b micom 7 mdat5_bi micom data bus b micom 8 mdat4_bi micom data bus b micom 9 mdat3_bi micom data bus b micom 10 mdat2_bi micom data bus b micom 11 mdat1_bi micom data bus b micom 12 mdat0_bi micom data bus b micom 13 dvdd digital power (+5v) 14 xti_in system clock input for 26.16mhz i xtal 15 xto_out system clock output for 26.16mhz o xtal 16 dvss digital gnd (0v) 17 dd15_bi dram data bus b dram 18 dd0_bi dram data bus b dram 19 dd14_bi dram data bus b dram 20 dd1_bi dram data bus b dram 21 dvss digital gnd (0v) 22 dd13_bi dram data bus b dram 23 dd2_bi dram data bus b dram 24 dd12_bi dram data bus b dram 25 dd3_bi dram data bus b dram 26 dvdd digital power (+5v) 27 dd11_bi dram data bus b dram 28 dd4_bi dram data bus b dram 29 dd10_bi dram data bus b dram 30 dd5_bi dram data bus b dram 31 dvss digital gnd (0v) 32 dd9_bi dram data bus b dram 33 dd6_bi dram data bus b dram 34 dd8_bi dram data bus b dram 35 dd7_bi dram data bus b dram
dvdp data processor ic KS1453 5 36 dvss digital gnd (0v) 37 zlcas_out dram low column address strobe o dram 38 zucas_out dram upper column address strobe o dram 39 zwe1_out dram write enable 1 (8m only) o dram 40 zwe0_out dram write enable 0 (4m, 8m, 16m) o dram 41 zoe1_out dram output enable 1 (dadr9 in 16m mode) o dram 42 dvdd digital power (+5v) 43 zoe0_out dram output enable 0 o dram 44 zras_out dram row address strobe o dram 45 dadr8_out dram address bus o dram 46 dadr7_out dram address bus o dram 47 dvss digital gnd (0v) 48 dadr0_out dram address bus o dram 49 dadr6_out dram address bus o dram 50 dadr1_out address bus o dram 51 dadr5_out dram address bus o dram 52 dadr2_out dram address bus o dram 53 dadr4_out dram address bus o dram 54 dadr3_out dram address bus o dram 55 dvss digital gnd (0v) 56 dvss digital gnd (0v) 57 tos_out top of sector o av decoder 58 datack_out data acknowledge signal output o av decoder 59 dvdd digital power (+5v) 60 sdata0_out dvd data/cd data bit stream (cdata) o av decoder 61 sdata1_out dvd data/cd data l/r clock (lrck) o av decoder 62 sdata2_out dvd data/cd data bit clock (blck) o av decoder 63 sdata3_out dvd data/cd data error plug (c2po) o av decoder 64 sdata4_out dvd data/sub-code serial data (sqdt) o av decoder 65 sdata5_out dvd data/sub-code frame sync (wfsy) o av decoder 66 sdata6_out dvd data/sub-code block sync (s0s1) o av decoder 67 sdata7_bi dvd data/sub-code serial clock (sqck) b av decoder 68 dvss digital gnd (0v) 69 cstrobe_out data strobe (clock) output o av decoder 70 datreq_in data request from a/v decoder or rom ecuador i av decoder 71 dter_out dvd data error output o av decoder 72 dvss digital gnd (0v) table 1. pin description (continued) no pin name description i/o note
KS1453 dvdp data processor ic 6 73 pwmo7_out pwm output signal o rf 74 pwmo6_out pwm output signal o rf 75 pwmo5_out pwm output signal o rf 76 pwmo4_out pwm output signal o rf 77 dvdd digital power (+5v) 78 pwmo3_out pwm output signal o rf 79 pwmo2_out pwm output signal o rf 80 pwmo1_out pwm output signal o rf 81 pwmo0_out pwm output signal o rf 82 dvss digital gnd (0v) 83 dvss digital gnd (0v) 84 dvss digital gnd (0v) 85 dvdd digital power (+5v) 86 dvdd digital power (+5v) 87 dvss digital gnd (0v) 88 dvss digital gnd (0v) 89 dvss digital gnd (0v) 90 dvss digital gnd (0v) 91 frsyz_out frame sync out o monitor 92 tx_out digital out (3-state) o monitor 93 gfs_out good frame sync detection status output (ok at h) o monitor 94 dvss digital gnd (0v) 95 ck33mi_in system clock input for 33.8688mhz i xtal 96 ck33mo_out system clock output for 33.8688mhz o xtal 97 dvdd digital power (+5v) 98 test0_in test mode select signal, pull_down pin i 99 test1_in test mode select signal, pull_down pin i 100 test2_in test mode select signal, pull_down pin i 101 efmo_out efm out o monitor 102 wfck_out write frame pulse o monitor 103 rfck_out reference frame pulse o monitor 104 plck_in phase locked clock i servo 105 dvss digital gnd (0v) 106 plllock_out lock signal for pll o servo 107 clvlock_out lock signal for clv o monitor 108 serlock_out lock signal for servo o servo 109 mdp_out spindle motor phase control signal (3-state) o servo table 1. pin description (continued) no pin name description i/o note
dvdp data processor ic KS1453 7 110 mds_out spindle motor speed control signal (3-state) o servo 111 dvss digital gnd (0v) 112 dvss digital gnd (0v) 113 mon_out spindle motor on/off control output o servo 114 fg_in reference signal for cav i servo 115 fsw_out spindle motor output filter conversion output (3-state) o servo 116 efmi_in efm/efm + signal input i servo 117 dvdd digital power (+5v) 118 dvdd digital power (+5v) 119 dvdd digital power (+5v) 120 ck16m_out ck33m's 1/2 clock/16.9344mhz o monitor 121 dempha_out deemphasis on when ?high? o monitor 122 test3_in test mode select signal, pull_down in i 123 dvss digital gnd (0v) 124 zrst_in hardware reset (active low) pull_up pin i micom 125 zwait_out micom read/write access wait (wait at l) o micom 126 zirqzd_out interrupt request to micom o micom 127 mrd_in micom read strobe (active low) pull_up pin i micom 128 mwr_in micom write strobe (active low) pull_up pin i micom table 1. pin description (continued) no pin name description i/o note
KS1453 dvdp data processor ic 8 2 electrical characteristics dc characteristics (v dd = 5.0v 5%, v ss = 0v, ta = 0 - +70 c) notes: 1. all cmos input signals, bidir pad's input mode signals 2. all output signals 3. all cmos input signals, bidir pad's input mode signals 4. all input signals with pull-down 5. all input signals with pull-up item conditions min max unit note input voltage input voltage ?h? level vih - 0.7v dd - v 1 input voltage ?l? level vil - - 0.3v dd v output voltage output voltage ?h? level voh ioh = -2, -4ma 2.4 v dd v 2 output voltage ?l? level vol iol = 2, 4ma 0 0.4 v input voltage input voltage ?h? level iih1 vin = v dd -10 10 m a 3 input voltage ?l? level iil1 vin = v ss -10 10 m a input voltage input voltage ?h? level iih2 vin = v dd 10 100 m a 4 input voltage ?l? level iil2 vin = v ss -100 -10 m a 5 input current leak i li v i = 0 - 5.25v -10 10 m a 1
dvdp data processor ic KS1453 9 absolute maximum ratings recommended operating conditions no item symbol spec unit 1 dc input voltage vin -0.3 - v dd + 0.3 v 2 c supply voltage v ddmax -0.3 - +7.0 v 3 c input current lin 10 ma 4 storage temperature tstg -40 - 125 c no item symbol spec unit 1 operating temperature topr 0 - 70 2 dc supply voltage v dd 4.75 - 5.25 v
KS1453 dvdp data processor ic 10 3 blcok characteristics ecc feature euclid's algorithm used. same circuit used for dvd and cd. dvd (primitive polynomial: x8 + x4 + x3 + x2 + 1) : error correcting ability for dvd data. ? pi (182, 172, 11) code: 5 error correct/10 errata correct ? po (208, 192, 17) code: 8 error correct/16 errata correct 38.8688mhz clock: 1x operation (pi+po+pi)/1 efm block satisfaction ? basic operation cd (primitive polynomial: x8 + x4 + x3 + x2 + 1) ? c1 (32, 28, 5) code: 2 error correct ? c2 (28, 24, 4) code: 2 error correct/4 errata correct repeat correction carried at for video-cd (c1 ? c2 ? c1 ? c2)
dvdp data processor ic KS1453 11 memory control feature cd data processor and dvd data processor has an external 4m or 8m dram in common. efm data write, ecc data r/w, descrambler r/w, and transfer read addressing feature. dvd ? 33.8688mhz crystal clock used. ? continuous storage according to input order regardless of data format (po deinterleave). ? 13 ecc block areas guaranteed in 4m bit dram. (efm, ecc, descrambler, and transfer cyclically processed) ? micom user area guaranteed (can use blocks 1 - 8 selectively in units of ecc blocks) ? efm data write in units of sectors. ? data transfer in units of sectors. ? block copy feature (sector number selection possible) ? micom direct access on dram cd ? cd-da, cd-rom, v-cd: 33.8688mhz crystal clock used. ? video-cd: repeat correction possible. ? 8kbyte memory area used. ? ef m, ecc, transfer feature. ? efm: referenced by wfck. ? ecc, transfer: referenced by rfck. ? micom direct access on dram. figure 3. block diagram of memory control efm efm + demodulator dram control - eccmem - dvdmem - cdmem micom ecc transfer dscramble & edc external 4m bit dram
KS1453 dvdp data processor ic 12 descrambler & edc & transfer feature ? descramble on/off control possible in micom ? edc flag output to micom ? 2048-byte or 2064-byte output selection possible ? transfer sector number selection possible ? maximum transfer rate: 5.4mbytes/s. ? parallel synchronous i/f support ? request, tos, ack, datclk, and edcflg's active ?l/h? selection possible. figure 4. block diagram of the transfer part dram transmission address generator micom i/f descrambler data transmitter edc & built-in sram req, tos, ack, datclk with css micom setting value transmission enable signal dram control signal descramble data dram data edcflg
dvdp data processor ic KS1453 13 cd audio feature receives data that has been completely corrected of errors in units of byte, and outputs it serially. interpolation, mute, and attenuation carried out for cd-da. subcode i/f feature cd graphic processing subcode data (p, q, r, s, t, u, v, w) is serially output. errors existing in the disc controlling subcode data (q) are checked and output. (p(x) = x16 + x12 + x5 + 1) micom i/f feature address/command data: 1byte write register access : cs enable ? w_reg address write ? command data write ? cs disable read register access : cs enable ? r_reg address write ? r_reg data read ? cs disable efm demodulator feature cd player, cd-rom, and dvd player mode demodulator : efm + demodulation (dvd) efm demodulation (cd) id sync, frame sync detection/protection/insertion : 4 step id sync/frame sync protection window section select 4 step id sync/ frame sync insertion frame number select sid error correction id (frame) sync continuous check
KS1453 dvdp data processor ic 14 4 micom register micom write register & read/write register table 2. micom write register & read/write register table (r/w unmarked; w) name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved (00 - 09) intctl1 0a dvdien dsien tosen tscmpen eccien emptyen overen underen intctl2 0b sbqien mcpen - - - - - - intctl3 0c - - - ifrq2 ifrq1 ifrq0 - clrint syscont1 0d mreset - - rcf1 rcf0 disc2 disc1 disc0 user1con 0e widewin gfspro syncdec isprot fnadj rfncon - - user2con of abth7 abth6 abth5 ab th4 abth3 abth2 abth1 abth0 dvddset 10 - - fwsel1 fwsel0 fgsel1 fgsel0 igsel1 igsel0 dvdcontr ol1 11 dscren strst - - insen wnden wndrt fclds dvdcontr ol2 12 wrst trst eccst ecneglt ecmod2 ecmod1 ecmod0 mcpst clvcontr ol1 13 pgain1 pgain0 sgain1 sgain0 - - - - clvcontr ol2 14 mdscon1 mdscon0 pllc1 pllc0 - mdpc p_res1 p_res0 clvcontr ol3 15 falthr1 falthr1 risthr1 risthr0 refsel servoc clvc1 clvc0 clvmode 16 sdwp sdwb - - sdcm3 sdcm2 sdcm1 sdcm0 reserved (17 - 18) trmode 19 ifmod2 ifmod1 ifmod0 - cdif0 drate - dvdif0 cdspeed 1a - - - - - cdspd2 cdspd1 cdspd0 cdmutcnt 1b cbitin2 cbitin1 cbitin0 dgoen dempha mute zcmt attn cdcontr ol 1c - - - - bypass infr t3_sel t3_mode eccreg1 1d eramodf eramodl maxmode2f maxmode2l c2eccf c2eccl c2err onlyf c2err onlyl eccreg2 1e - cdecc eccmode c2fgtype [4] c2fgtype [3] c2fgtype [2] c2fgtype [1] c2fgtype [0] eccreg3 1f - - - - setflg [3] setflg [2] setflg [1] setflg [0] address setting on micom direct access buffer mode (read/write) wadrh 20 - - - adr20 adr19 adr18 adr17 adr16 wadrm 21 adr15 adr14 adr13 adr12 adr11 adr10 adr9 adr8 wadrl 22 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 data write to buffer (when mdab = 1)
dvdp data processor ic KS1453 15 wdata 23 wdt7 wdt6 wdt5 wdt4 wdt3 wdt2 wdt1 wdt0 reserved (24 - 2f) buffering start sector unit number wbah 30 - - - - - - b9 b8 wbal 31 b7 b6 b5 b4 b3 b2 b1 b0 ecc start block unit number weah 32 - - - - - - b9 b8 weal 33 b7 b6 b5 b4 b3 b2 b1 b0 transfer start sector unit number wtah 34 - - - - - - b9 b8 wtal 35 b7 b6 b5 b4 b3 b2 b1 b0 over threshold size (number of sector units) (read/write) otsh 36 - - - - - - b9 b8 otsl 37 b7 b6 b5 b4 b3 b2 b1 b0 under threshold size (number of sector units) (read/write) utsh 38 - - - - - - b9 b8 utsl 39 b7 b6 b5 b4 b3 b2 b1 b0 number of transfer sectors select (read/write) tnh 3a b15 b14 b13 b12 b11 b10 b9 b8 tnl 3b b7 b6 b5 b4 b3 b2 b1 b0 size of buffer for micom use select (read/write) mbs 3c - - - - b3 b2 b1 b0 decoder direct data block copy source sector address select bcpsh 3d - - - - - - b9 b8 bcpsl 3e b7 b6 b5 b4 b3 b2 b1 b0 reserved (3f) decoder direct data block copy target sector address select bcpth 40 - - - - - - b9 b8 bcptl 41 b7 b6 b5 b4 b3 b2 b1 b0 descramble start sector unit number wdah 42 - - - - - - b9 b8 wdal 43 b7 b6 b5 b4 b3 b2 b1 b0 table 2. micom write register & read/write register table (r/w unmarked; w) (continued) name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
KS1453 dvdp data processor ic 16 reserved (44 - 49) userreg reserved (a0 - a7) a8 - - tstwrd ectest - - - - reserved (a9) aa monitor3 monitor2 monitor1 monitor0 mprstz tstendm ux tstpore nd tstpiren d reserved (ab - ad) ae regeg ackeg streg toseg dtreg - tstid tstidsy reserved (af - bf) c0 pwm07 pwm06 pwm05 pwm04 pwm03 pwm02 pwm01 pwm00 c1 pwm17 pwm16 pwm15 pwm14 pwm13 pwm12 pwm11 pwm10 c2 pwm27 pwm26 pwm25 pwm24 pwm23 pwm22 pwm21 pwm20 c3 pwm37 pwm36 pwm35 pwm34 pwm33 pwm32 pwm31 pwm30 c4 pwm47 pwm46 pwm45 pwm44 pwm43 pwm42 pwm41 pwm40 c5 pwm57 pwm56 pwm55 pwm54 pwm53 pwm52 pwm51 pwm50 c6 pwm67 pwm66 pwm65 pwm64 pwm63 pwm62 pwm61 pwm60 c7 pwm77 pwm76 pwm75 pwm74 pwm73 pwm72 pwm71 pwm70 c8 cavcksel 1 cavcksel 0 - - - cavval 10 cavval 9 cavval 8 c9 cavval7 cavval6 cavval5 cavval4 cavval3 cavval2 cavval1 cavval0 reserved (ca - df) reserved (e0 - ef) table 2. micom write register & read/write register table (r/w unmarked; w) (continued) name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
dvdp data processor ic KS1453 17 micom read register & read/write register table 3. micom read register & read/write register table (r/w unmarked; r) name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 intstat1 4a dvdsint dsint tosint trscmplt eccmplt empty over under intstat2 4b sbqint mcpint - - - - - - errstat 4c eiderr dsierr idconerr - eccerr edcflg - sbqerr dvdstatus 4d - - - - syok nosy ilsy - dvdsvstat 4e - lock gfs - - - - - reserved (4f) cdsubq 50 sbq79 sbq78 sbq77 sbq76 sbq75 sbq74 sbq73 sbq72 59 sbq07 sbq06 sbq05 sbq04 sbq03 sbq02 sbq01 sbq00 reserved (5a - 5f) seekidadr 60 sid31 sid30 sid29 sid28 sid27 sid26 sid25 sid24 61 sid23 sid22 sid21 sid20 sid19 sid18 sid17 sid16 62 sid15 sid14 sid13 sid12 sid11 sid10 sid09 sid08 63 sid07 sid06 sid05 sid04 sid03 sid02 sid01 sid00 transidadr 64 tid31 tid30 tid29 tid28 tid27 tid26 tid25 tid24 65 tid23 tid22 tid21 tid20 tid19 tid18 tid17 tid16 66 tid15 tid14 tid13 tid12 tid11 tid10 tid09 tid08 67 tid07 tid06 tid05 tid04 tid03 tid02 tid01 tid00 reserved (68 - 6f) address reading on micom direct access buffer mode (read/write) radrh 70 - - - adr20 adr19 adr18 adr17 adr16 radrm 71 adr15 adr14 adr13 adr12 adr11 adr10 adr9 adr8 radrl 72 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 data read from buffer rdata 73 rdt7 rdt6 rdt5 rdt4 rdt3 rdt2 rdt1 rdt0 reserved (74 - 7f) buffering end sector unit number rwah 80 - - - - - - b9 b8 rwal 81 b7 b6 b5 b4 b3 b2 b1 b0 ecc end sector unit number reah 82 - - - - - - b9 b8 real 83 b7 b6 b5 b4 b3 b2 b1 b0 transferring end sector unit number rtah 84 - - - - - - b9 b8 rtal 85 b7 b6 b5 b4 b3 b2 b1 b0 dsi unit number dsih 86 - - - - - - b9 b8 dsil 87 b7 b6 b5 b4 b3 b2 b1 b0 descramble end sector unit number rdah 88 - - - - - - b9 b8 rdal 89 b7 b6 b5 b4 b3 b2 b1 b0
KS1453 dvdp data processor ic 18 reserved (8a - 93) ecc end id address eeida 94 id31 id30 id29 id28 id27 id26 id25 id24 95 id23 id22 id21 id20 id19 id18 id17 id16 96 id15 id14 id13 id12 id11 id10 id09 id08 97 id07 id06 id05 id04 id03 id02 id01 id00 reserved (98 - 9b) dsi id address dsida 9c id31 id30 id29 id28 id27 id26 id25 id24 9d id23 id22 id21 id20 id19 id18 id17 id16 9e id15 id14 id13 id12 id11 id10 id09 id08 9f id07 id06 id05 id04 id03 id02 id01 id00 remaining data size (number of sector units) rdsh f0 - - - - -- - b9 b8 rdsl f1 b7 b6 b5 b4 b3 b2 b1 b0 reserved (f2 - ff) table 3. micom read register & read/write register table (r/w unmarked; r) (continued) name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
dvdp data processor ic KS1453 19 micom register description micom write register & read/write register (r/w unmarked; w) < dvd interrupt masking register > ? dvdien: dvd id-sync interrupt request enable enable/disable control bit of the id-sync interrupt generated in the dvd decoder. 1: enable 0: disable ? dsien: dsi interrupt 1: enable 0: disable ? tosen: top of sector interrupt request enable enable/disable control bit of the interrupt that marks the first data in the sector being transferred from the dvd decoder to the a/v decoder or host. 1: enable 0: disable ? tscmpten: transfer complete interrupt request enable control bit for interrupt signal generation when transfer is complete for the number of bytes demanded in dvd rom application (tnh, l). 1: enable 0: disable ? eccien: ecc complete interrupt request enable enable/disable control bit of the ecc complete interrupt generated in the dvd decoder. 1: enable 0: disable ? emptyen: buffer memory empty interrupt (for transfer) request enable 1: enable 0: disable ? overen: buffer memory over interrupt request enable interrupt request enable generated when the filled area in the buffer memory is more than the over threshold size (ots) set by micom (hysteresis). 1: enable 0: disable ? underen: buffer memory under interrupt request enable interrupt request enable generated when the filled area in the buffer memory is less than the under threshold size set by micom (hysteresis). 1: enable 0: disable intctl1: interrupt control register 1 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0a dvdien dsien tosen tscmpten eccien emptyen overen underen reset value 0 0 0 0 0 0 0 0
KS1453 dvdp data processor ic 20 < cd interrupt masking register > ? sbqien: cd subcode-sync interrupt request enable enable/disable control bit for subcode-sync interrupt generated in the cd decoder. 1: enable 0: disable ? mcpen: micom block copy mode 1: enable 0: disable ? ifrq2 - 0: interrupt request frequency select register (only applicable to dvdsint) ? clrint: interrupt clear register decides whether or not to clear the interrupt status register after micom has read it. 1: clear 0: don't clear intctl2: interrupt control register 2 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0b sbqien mcpen - - - - - - reset value 0 0 - - - - - - intctl3: interrupt control register 3 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0c - - - ifrq2 ifrq1 ifrq0 - clrint reset value - - - 0 0 0 - 1 ifrq2 ifrq1 ifrq0 number of interrupts/number of id sectors 0 0 0 1/1 id sector 0 0 1 1/2 id sectors 0 1 0 1/4 id sectors 0 1 1 1/8 id sectors 1 0 0 1/16 id sectors other reserved
dvdp data processor ic KS1453 21 ? mreset: master reset ? reset z-decoder. (setting all registers to predefined reset value. same as zrst) the decoder automatically sets to "1" after micom turns on the reset. 0: reset on, 1: reset off ? rcf1 - 0: ram configuration ? buffer size select. ? z-decoder control register. disc2 - 0: shows the operating disc type. syscont1: system control register 1 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0d mreset - - rcf1 rcf0 disc2 disc1 disc0 reset value 1 - - 0 0 1 0 0 rcf1 rcf0 dram configuration 0 0 4mbits 0 1 8mbits 1 0 n.a 1 1 16mbits disc2 disc1 disc0 disc type 1 0 0 dvd 1 1 0 dvd-rom 0 0 0 cd-da 0 0 1 v-cd 0 1 0 cd-rom other reserved
KS1453 dvdp data processor ic 22 ? widewin: sync protection window control h ? if frame sync doesn't occur for more than the insertion number (n) designated by the protection window, again set the widest protection window for sync detection. if sync is detected, immediately correct to that value and protect to the window with the selected width. if sync isn't detected, immediately cancel window. l ? find sync by immediately cancelling the protection window without wide window operating mode. ? gfspro: good frame sync detecting conditions h ? complete match between detected sync and inserted sync l ? a 1 difference between detected sync and inserted sync ? syncdec: frame sync detecting conditions h ? sync detect by sync code (32bit) l ? sync detect using specified pattern (22bit) ? isprot: id sync protection starting conditions h ? immediately start id sync protection when sector sync is detected. l ? id sync protection is started when id sync is detected in the expected frame after frame sync protection has begun. frame number (fn) match:/s0 detected in fn0 set to low after system reset. ? fnadj: frame number (address) correcting conditions h ? correct counter value within a 5 difference between the detected frame number and frame counter value. l ? correct counter value within a 2 difference. valid conditions: frame sync continuity must be maintained. if continuity isn't maintained, it is changed to insertion mode. ? rfncon: frame number correction to the detected value. h ? frame number correction (if detected frame number is continuous for more than 3 times) l ? frame number correction (according to fnadj conditions) valid conditions: frame sync continuity must be maintained. if continuity isn't maintained, it is changed to insertion mode. usercont1: user control register1 (sync control) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0e widewin gfspro syncdec isprot fnadj rfncon - - reset value 1 1 1 0 1 1 - -
dvdp data processor ic KS1453 23 ? bth[7:0] : flag generated if the absolute value of the input data difference (|l0-l1|) is larger than the set abth value during l-ch/ r-ch data serial output. : if the flag pattern is 0 0 1 1 0 0 ? flag |l0-l1| |l1-l2| |l2-l3| |l3-l4| |l4-l5| |l5-l6| ? data ? l3 = (l2+l4)/2 0 0 1 1 1 0 ? flag |l0-l1| |l1-l2| |l2-l3| |l3-l4| |l4-l5| |l5-l6| ? data ? l3 = (l2+l5)/2, l4 = (l3+l5)/2 usercont2: user con. register2 (channel clock pll control) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0f abth7 abth6 abth5 abth4 abth3 abth2 abth1 abth0 reset value 1 1 1 1 0 0 0 0
KS1453 dvdp data processor ic 24 ? fwsel1 - 0: frame sync protection window section select ? fgsel1 - 0: number of frame sync inserted frames ? igsel1 - 0: number of id sync inserted sectors dvddset: dvd decoder set (sync detect conditions) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10 - - fwsel1 fwsel0 fgsel1 fgsel0 igsel1 igsel0 reset value - - 0 0 0 0 0 0 fwsel1 fwsel0 frame sync protection window (dvd) frame sync protection window (cd) 0 0 6 clocks 3 clocks 0 1 12 clocks 6 clocks 1 0 20 clocks 10 clocks 1 1 24 clocks 12 clocks fgsel1 fgsel0 number of frame sync inserted frames 0 0 4 frames 0 1 13 frames 1 0 16 frames 1 1 28 frames igsel1 igsel0 number of id sync inserted sectors 0 0 1 sector 0 1 2 sectors 1 0 3 sectors 1 1 4 sectors
dvdp data processor ic KS1453 25 ? dscren: descramble on/off 1: descramble on 0: descramble off ? strst: forced tr mode cancellation 1: cancel 0: normal ? insen: insert enable 1: carry out frame, id sync insertion. 0: don't carry out sync insertion. ? wnden: window enable (frame) 1: enable sync protection window. sync detected outside the window is illegal, and isn't used in resets such as insertion timing. if illegal syncs are consecutively found n times, the protection window is reset and opened. 0: open the window and make all detected syncs valid. ? wndrt: window reset window is opened if this bit is 1. it is used when you want to lock the window quickly by detecting new sync during track jump. ? fclds: frame counter value load conditions 1: load the frame counter value continuously detected while continuity was being maintained. 0: load the frame counter value detected within the frwin section while continuity was being maintained. in other sections, load the inserted frame counter. dvdcontrol1: dvd decoder (sync) control register 1 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11 dscren strst - - insen wnden wndrt fclds reset value 1 0 - - 1 1 0 1
KS1453 dvdp data processor ic 26 ? wrst: enables/disables efm demodulated data write to the buffer. 1: buffer write enable 0: buffer write disable ? trst: data transfer enable/disable from the buffer to the a/v decoder or host. 1: transfer enable 0: transfer disable ? eccst: error correction enable/disable. 1: error correction enable 0: error correction disable ? ecneglt: disregard error correction (used when error still remains in an ecc completed block, but micom decides an ecc retry isn't necessary.) 1: repeat error correction (until ecc stop {eccst = ?0?} or {ecneglt = ?1?}) 0: disregard error correction (skip current correction block and move to next block.) ? ecmod2 - 0: error correction mode select in repeat correction mode (ecmod2 = ?1?), if errors still exist after correction and there is enough buffer space, ecc is automatically retried until the eccneglt signal is input. (buffer space is determined by micom) ? mcpst: micom block copy start command when it is ?1?, the decoder automatically moves 1 sector of data in the micom-selected address. mcpend is output when the operation is complete, and micom resets the mcpst bit to ?0?. dvdcontrol2: dvd control register 2 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 12 wrst trst eccst ecneglt ecmod2 ecmod1 ecmod0 mcpst reset value 0 0 0 0 0 1 0 0 ecmod2 ecmod1 ecmod0 disc speed 0 0 0 no error correction 0 0 1 pi+po 0 1 0 pi+po+pi (normal) 0 1 1 pi+po+pi+po 1 0 0 repeat correction (pipo) 1 0 1 reserved 1 1 x
dvdp data processor ic KS1453 27 ? pgain(1:0): dvd/cd clv's mdp gain select ? sgain(1:0): dvd/cd clv's mds gain select and cav control's mds gain select. clvcontrol1: clv control register 1 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 13 pgain1 pgain0 sgain1 sgain0 - - - - reset value 0 0 0 0 - - - - pgain1 pgain0 mdp gain 0 0 -6db 0 1 -12db 1 0 -18db 1 1 0db sgain1 sgain0 mds gain 0 0 -6db 0 1 -12db 1 0 -18db 1 1 0db
KS1453 dvdp data processor ic 28 ? mdscon(1:0): dvd/cd clv's mds linear motion range select ? pllc(1:0): threshold value select for dvd/cd pll lock signal cancellation ? mdpc: mdp output select outside of mds linear range ? pres(1:0): wfck/rfck reference signal for mdp select within clvp mode of dvd/cd clv clvcontrol2: clv control register 2 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 14 mdscon1 mdscon0 pllc1 pllc0 - mdpc pres1 pres0 reset value 0 0 0 0 - 0 0 0 mdscon1 mdscon0 linear range dvdrom cdrom 0 0 9% 4.5% 0 1 18% 9% 1 0 36% 18% 1 1 reserve 33% pllc1 pllc0 threshold 0 0 pll lock falling after wfck 16 0 1 pll lock falling after wfck 32 1 0 pll lock falling after wfck 64 1 1 pll lock falling after wfck 128 mdpc operation 0 error signal output outside the mds linear range 1 hi-z output outside the mds linear range pres1 pres0 wfck standard rfck standard 0 0 wfck/2 rfck/2 0 1 wfck/4 rfck/4 1 0 wfck/8 rfck/8 1 1 wfck/16 rfck/16
dvdp data processor ic KS1453 29 ? falthr(1:0): dvd/cd's clv lock signal falling time select ? risthr(1:0): dvd/cd's clv lock signal rising time select ? refsel: dvd/cd's clv lock signal generating gfs sample signal select ? servoc: dvd/cd's servo lock signal falling time select rising is carried out if gfs is detected twice in a row in rfck standard. ? clvc(1:0): mode select for dvd/cd's clv lock on/off clv lock decision signal in wide mode: gfs clv lock decision signal in narrow mode: gfs narrow the narrow signal means the pll operates within the linear range selected by mdscon(1:0). narrow means gfs = high, and the 'not saturated' condition. clvcontrol3: clv control register 3 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 15 falthr1 falthr0 risthr1 risthr0 refsel servoc clvc1 clvc0 reset value 0 0 0 0 0 0 0 0 falthr1 falthr0 threshold 0 0 clv lock falling after wfck/rfck 32 0 1 clv lock falling after wfck/rfck 64 1 0 clv lock falling after wfck/rfck 128 1 1 clv lock falling after wfck/rfck 256 risthr1 risthr0 threshold 0 0 clv lock rising after wfck/rfck 1 0 1 clv lock rising after wfck/rfck 2 1 0 clv lock rising after wfck/rfck 4 1 1 clv lock rising after wfck/rfck 8 refsel clv lock reference signal 0 wfck 1 rfck servoc threshold 0 servo lock falling after rfck 64 1 servo lock falling after rfck 128 clvc1 clvc2 clvlock on (active high) clvlock off (active low) 0 0 wide wide 0 1 wide narrow 1 0 narrow wide 1 1 narrow narrow
KS1453 dvdp data processor ic 30 ? sdwp: small section sample signal 0: sample every rfck/4 1: sample every rfck/2 ? sdwb: large section sample signal 0: sample every rfck/32 1: sample every rfck/16 ? sdcm3 - sdcm0: clv mode select mdp must output to hi-z in stop mode. clvmode: clv mode register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 16 sdwp sdwb - - sdcm3 sdcm2 sdcm1 sdcm0 reset value 1 1 - - 0 0 0 0 sdcm3 sdcm2 sdcm1 sdcm0 clv mode mdp block mds block 0 0 0 0 stop hi-z hi-z 1 0 0 0 kick h hi-z 1 0 1 0 brak l hi-z 1 1 1 0 clvs l,z,h hi-z 1 1 0 0 clvh l,z,h hi-z 1 1 1 1 clvp l,z,h l,h 0 1 1 0 clva l,z,h l,z,h 1 0 0 1 cav hi-z l,z,h other reserve
dvdp data processor ic KS1453 31 ? ifmod2 - 0: transfer i/f method to a/v decoder or rom decoder select ? cdif0: cd interface format select ? drate: transfer speed to a/v decoder or rom decoder select 1: byte/240ns 0: byte/480ns fixed to byte/240ns in dvd-rom mode. ? dvdif0: dvd interface format select ? cd speed control register trmode: data transfer mode register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 19 ifmod2 ifmod1 ifmod0 - cdif0 drate - dvdif0 reset value 0 0 0 - 0 1 - 1 ifmod2 ifmod1 ifmod0 transfer i/f method 0 0 0 c (a/v decoder: synchronous) - - - reserved cdif0 transfer format 0 format 1 1 format 2 dvdif0 transfer format transfer data 0 mode 1 2048 bytes main 1 mode 2 2064 bytes sector cdspeed: cd speed control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1a - - - - - cdspd2 cdspd1 cdspd0 reset value - - - - - 0 0 0 cdspd2 cdspd1 cdspd0 disc speed 0 0 0 1x 0 0 1 2x 0 1 0 4x other reserved
KS1453 dvdp data processor ic 32 ? cbitin(2:0): digital audio output control mode select cbitin0 = 0: for common use (mode ii) cbitin1 = 0: audio cbitin2 = 0: digital copy prohibited, 1: digital copy possible ? dgoen: digital audio output mode select 0: hi-z 1: output ? dempha: cd audio's deemphasis control 0: deemphasis off 1: deemphasis on ? mute: cd-da data mute 0: mute off 1: mute on ? zcmt: zero cross mute control bit 0: zero cross mute on 1: zero cross mute off ? attn: attenuation on/off 0: attenuation off 1: attenuation on cdmutcnt: cd mute control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1b cbitin2 cbitin1 cbitin0 dgoen dempha mute zcmt attn reset value 0 0 0 0 0 1 0 0 attn mute db 0 0 0 0 1 - 1 0 -12 1 1 -12
dvdp data processor ic KS1453 33 ? bypass: h: normal l-ch/ r-ch data serial output l: error value correcting circuit application. ? infr: decides whether to release the frame window right after the inserted frame number set by fgsel (1:0), or wait until after seeing a few more frame syncs detected by fwid. 0: release frame window right after the inserted frame number set by fgsel (1:0). inserted counter is reset by the frame sync detected first, and the frame window is locked again within a regular period. 1: don't release frame window right after the inserted frame number set by fgse (1:0). lock frame window when detected frame syncs are generated continuously within a regular period, after the inserted counter is reset by the frame sync detected first. ? t3_sel: when 2t is generated in the efm input data, and more than 4t of data is maintained before and after, decides the direction change that will increase data by 2t in either direction to change to 3t. h: increase to previous 4t data direction. l: increase to later 4t data direction. ? t3_mode: carry out 3t correction using efm input data h: on l: off cdcontrol: cd control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1c - - - - bypass infr t3_sel t3_mode reset value 0 0 0 0 1 1 0 0
KS1453 dvdp data processor ic 34 ? [eramodf] 1: erasure correction mode in dvd mode during max erasure generation erasure correction mode in cd-first-c2 mode during max erasure generation 0: erasure correction mode in dvd mode during max erasure generation erasure correction mode in cd-first-c2 mode during max erasure generation ? [eramodl] there is no dvd mode. 1: erasure correction mode in cd-last-c2 mode during max erasure generation 0: erasure correction mode in cd-last-c2 mode during max erasure generation ? [maxmode2f] 1: don't error correct max erasure generation in dvd mode don't error correct max erasure generation in cd-first-c2 mode 0: error correct max erasure generation in dvd mode error correct max erasure generation in cd-first-c2 mode ? [maxmode2l] there is no dvd mode. 1: don't error correct max erasure generation in cd-last-c2 mode 0: error correc2eccf] there is no dvd mode ? [c2eccf] there is no dvd mode 1: don't error correct overflow generation in cd-first-c2 mode 0: error correct overflow generation in cd-first-c2 mode ? [c2eccl] there is no dvd mode 1: don't error correct overflow generation in cd-last-c2 mode 0: error correct overflow generation in cd-last-c2 mode ? [c2erronlyf] 1: only error correct in cd-first-c2 mode (ignore flag) 0: error correct in cd-first-c2 mode (erasure or error) ? [c2erronlyl] 1: only error correct in cd-last-c2 mode 0: error correct in cd-last-c2 mode (erasure or error) ct max erasure generation in cd-last-c2 mode cdcontrol: cd control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1d eramof eramol maxmode 2f maxmode 2l c2eccf c2eccl c2erro onlyf c2erro onlyl reset value 1 1 0 0 1 1 0 0
dvdp data processor ic KS1453 35 ? [cdecc] repeat correction in cd mode (change name to existing vcdrep bit) 1: repeat correction 0: correct once ? [eccmode] 1: in cd repeat correction mode (cdecc = 1), don't correct errors in the firstsection, but correct the last section. 0: correct the errors in both the first and last sections in cd repeat correction mode. ? c2fgtype[4:0] flag setting condition select in cd mode c2fgtype[4]; 1: if maxmodc2f/maxmodc2l = ?1? in cd-c2 mode, c1 flag copy [11] 0: if maxmodc2f/maxmodc2l = ?1? in cd-c2 mode, c2 flag out [01] ? c2fgtype[3]; 1: if an overflow occurs in cd-c2 mode, c1 flag copy [11] 0: if an overflow occurs in cd-c2 mode, c2 flag out [01] ? c2fgtype[2]; cd repeat correction mode 1: max correcting (both error and erasure) in cd-last-c2 mode, c1 flag copt [11] ? default 0: max correcting (both error and erasure) in cd-last-c2 mode, c2 flag out [01] ? c2fgtype[1]; cd one time correction mode 1: max correcting (both error and erasure) in cd-c2 mode, c1 flag copt [11] ? default 0: max correcting (both error and erasure) in cd-c2 mode, c2 flag out [01] ? c2fgtype[0]; 1: uncorrectable code in cd-c2 mode, c1 flag copy [11] 0: uncorrectable code in cd-c2 mode, c2 flag out [01] cdcontrol: cd control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1e - cdecc eccmode c2fgtype [4] c2fgtype [3] c2fgtype [2] c2fgtype [1] c2fgtype [0] reset value - 1 0 1 1 1 1 1
KS1453 dvdp data processor ic 36 ? setflg[3:0] setflg[3]; - pi flag in dvd mode 1: flag setting only when correction is impossible. (error or erasure) ? must be 'default' - c1-first flag in cd mode 1: flag setting only when correction is impossible (more than 2 errors) 0: flag setting even during 2 error correction ? setflg[2]; - po flag in dvd mode 1: flag setting only when correction is impossible (error or erasure) ? must be 'default' - c2-first flag in cd mode 1: flag setting only when correction is impossible (more than 2 errors) ? must be 'default' ? setflg[1]; no dvd mode. c1-last flag in cd mode. 1: flag setting only when correction is impossible (more than 2 errors) 0: flag setting even during 2 error correction ? setflg[0]; no dvd mode. c1-last flag in cd mode. 1: flag setting only when correction is impossible (more than 2 errors) ? must be 'default' cdcontrol: cd control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1f - - - - setflg[3] setflg[2] setflg[1] setflg[0] reset value - - - - 1 1 1 1 wadrh/m/l: address setting on micom direct access buffer mode (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 20 - - - adr20 adr19 adr18 adr17 adr16 21 adr15 adr14 adr13 adr12 adr11 adr10 adr9 adr8 22 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 wdata: data write to buffer (when mdab = 1) 23 wdt7 wdt6 wdt5 wdt4 wdt3 wdt2 wdt1 wdt0 reset value 20 - 23 register: all-zero
dvdp data processor ic KS1453 37 buffer writing figure 5. buffer writing zcs mrza mwr mrd mdat (7:0) *zwait $23 wdata1 wdata2 set register adr. $23 - store wdata1 (wdt7 ~ wdt0) value to $23 register. - zwait signal enable (low) until wdata1 is completely stored in the buffer. - when the zwait signal is disabled (high), micom prepares the next data for transfer (wdata2). - $23 register pointer doesn't change. wdata2 is stored in the register. - wadr ($20 ~ $22)'s buffer point (adr20 ~ 0) increases automatically. - enable the zwait signal until wdata2 is completely stored in the buffer pointer. micom stores the next value (wdata3, ..) in the register when zwait is high.
KS1453 dvdp data processor ic 38 last writed address reading read the buffer pointer value (+ 1) last written in the buffer. select the start sector unit number for storing efm data in the buffer. set w sector unit. select the sector unit number for error correction. (set in units of blocks with b3 - b0 = ?0?) set x sector unit. figure 6. last writed address reading buffering start sector unit number address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 30 b9 - b8 31 b7 - b0 reset value 3ff ecc start sector unit number address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 32 b9 - b8 33 b7 - b0 reset value 3ff zcs mrza mwr mrd mdat (7:0) $20 data ($21) data ($20) set register adr. $20 read $20 adr. register value - automatically change register pointer to $21 - read register value of $21
dvdp data processor ic KS1453 39 select sector unit number for starting data transfer. set z sector unit. the unit number above is automatically incremented in units of sectors when all applicable start signals are enabled and completed. unit number definition b9 - 8: bank 0 - 3 b7 - 4: block 0 - 12 b3 - 0: sector 0 - 15 set buffer memory's over threshold size (maximum 16 blocks). in other words, set the maximum allowable value for the absolute value of (unit number w-unit number z). when the section filled with memory is larger than the selected value, the z-decoder generates an over interrupt. set buffer memory's under threshold size (maximum 16 blocks). in other words, set the minimum allowable value for the absolute value of (unit number w - unit number z). when the section filled with memory is less than the selected value, the z-decoder generates an under interrupt. transfer start sector unit number address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 34 b9 - b8 35 b7 - b0 reset value 1ff over threshold size (sector unit number) (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 36 b9 - b8 37 b7 - b0 reset value all high under threshold size (sector unit number) (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 38 b9 - b8 39 b7 - b0 reset value all zero
KS1453 dvdp data processor ic 40 sets the number of bytes of the data to be transferred to the a/v decoder or rom decoder. maximum number of sectors to be transferred is 64k sectors. after trasferring the predetermined number of sectors, the z-decoder generates the transfer complete interrupt (trscmplt). select the size of the buffer for micom. the size is in units of ecc blocks (16kbytes), and a maximum of 8 blocks is possible in bank units. (lsb 4 bits: for dvds '0001'[block 1] - '1000' [block 8] for cds '0001' - '0111') the initial value is 1 block. bank: composed in units of 4 mbit. there are 4 banks in a 16m bit, so a buffer for micom with a maximum of 32 block (512k byte ? 4mbits) can be guaranteed. source sector address which is used in the mode that automatically moves the data to be used by micom within the buffer in units of sectors. target sector address which is used in the mode that automatically moves the data to be used by micom within the buffer in units of sectors. transfer sector number select (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 3a b15 - b8 3b b7 - b0 reset value all high buffer size for micom select (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 3c - - - - b3 b2 b1 b0 reset value - - - - 0 0 0 1 decoder direct block copy source sector address select (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 3d b9 - b8 3e b7 - b0 reset value all zero decoder direct block copy target sector address select (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 40 b9 - b8 41 b7 - b0 reset value all zero
dvdp data processor ic KS1453 41 set descramble starting sector unit number. the unit number is automatically incremented when all applicable start signals are enabled and completed in units of sector. unit number definition b9 - 8: bank 0 - 3 b7 - 4: block 0 - 12 b3 - 0: sector 0 - 15 ? tstwrd: for chip testing. ? ectest: for ecc block simulation (let it be in default state) ? monitor 3 - 0: for internal signal monitoring in chip test mode. ? mprstz: bunp, dunp, eunp, and tunp's initial value select register 1: tunp = "1ff" 0: bunp, dunp, eunp = "3ff" used for stopping a mode by force during ecc's operation (pi read or po read). when the operation is stopped, the next operation is carried out according to the specified ecc mode. in other words, if you stop the first pi process by force in pi+po+pi mode, the po mode is initiated, and if the po mode is stopped by force, the next pi is initiated. if you stop during the last pi process, the next ecc block's first pi process is initiated. ? stop operation: ? tstendmux bit set to ?1?. - tstpirend if pi. tstporend if po, set the bit to ?1?. ? stop the operation at this time. ? tstpirend or tstporend bit is set to?0?. set tstendmux bit to ?0? - ? and can be carried out simultaneously. descramble start sector unit number (read/write) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 42 b9 - b8 43 b7 - b0 reset value 1ff userreg address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a8 - - tstwrd ectest - - - - reset value - - 0 0 - - - - usrreg: ecc operation control/memory point reset address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa monito r3 monito r2 monito r1 monito r0 mprstz tstend mux tstpor end tstpire nd reset value 0 0 0 0 1 0 0 0
KS1453 dvdp data processor ic 42 ? reqeg, ackeg, streg, toseg, dtereg selects the active mode of the transfer-related signals (datreq, datack, strobe, tos, dter). ? tstid, tstidsy for chip testing ? pwm output's high pulse width is capable of changing in 0 - 255 steps. ? resolution: xti1 1clk/step ? address: output pin usrreg: data transfer/test mode register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ae reqeg ackeg streg toseg dtereg - tstid tstidsy reset value 0 0 0 0 0 - 0 0 value reqeg ackeg streg toseg dtereg 1 active high active high falling edge active high active high 0 active low active low rising edge active low active low userreg: pwm register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c0 pwm07 pwm06 pwm05 pwm04 pwm03 pwm02 pwm01 pwm00 c1 pwm17 pwm16 pwm15 pwm14 pwm13 pwm12 pwm11 pwm10 c2 pwm27 pwm26 pwm25 pwm24 pwm23 pwm22 pwm21 pwm20 c3 pwm37 pwm36 pwm35 pwm34 pwm33 pwm32 pwm31 pwm30 c4 pwm47 pwm46 pwm45 pwm44 pwm43 pwm42 pwm41 pwm40 c5 pwm57 pwm56 pwm55 pwm54 pwm53 pwm52 pwm51 pwm50 c6 pwm67 pwm66 pwm65 pwm64 pwm63 pwm62 pwm61 pwm60 c7 pwm77 pwm76 pwm75 pwm74 pwm73 pwm72 pwm71 pwm70 reset value 1 0 0 0 0 0 0 0 address c7 c6 c5 c4 c3 c2 c1 c0 output pin pwmo7 pwmo6 pwmo5 pwmo4 pwmo3 pwmo2 pwmo1 pwmo0
dvdp data processor ic KS1453 43 ? cksel(1:0): reference clock select for cav control ? cavval(10:0): initial value select for cav control in cav mode, the disc rotating speed is set according to the following formula. disc rpm = fsys 10 nck / 1024 / cav_ref here, fsys: system clock for dvd (27mhz), for cd (33.8688/8mhz) nck: select clock division ratio using cavck[1:0] in other words, (8 ? 1/128, 4 ? 1/256, 2 ? 1/512, 1 ? 1/1024). cav_ref26.16: value defined by (1537- ncarv). has a range of 1408 cav_ref 1537. where xtal: dvd (xtl1), cd (ck33mi/8) example) cavval(10:0) value select for 1440 rpm the cav_ref value in the formula above can change depending on the fsys. cavcontrol: cav control register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8 cksel1 cksel0 - - - cavval1 0 cavval9 cavval8 c9 cavval7 cavval6 cavval5 cavval4 cavval3 cavval2 cavval1 cavval0 reset value 0 0 0 0 0 0 0 0 cavck(1) cavck(0) nck disc rotation number selection range dvd cd 0 0 8 1372.4 - 2746.5 215.2 - 430.7 0 1 4 686.2 - 1372.4 107.6 - 215.2 1 0 2 343.1 - 686.2 53.8 - 107.6 1 1 1 171.5 - 343.1 26.9 - 53.8 formual : cav _ ref xtal 10 nck 1024 rpm --------------------------------------------------- = cav _ ref 26.16 mhz 10 8 10241440 ------------------------------------------------------- 1419.271419 === cavvar 1537141911876 h == ? =
KS1453 dvdp data processor ic 44 micom read register & read/write register (r/w unmarked; r) ? dvdsint: dvd sync interrupt request set to '1' each time a sync (id sync) is output from the dvd decoder. this interrupt is generated when intctl3 ($0c)'s clrint bit is ?1?. it is cleared to ?0? when micom reads the bit of the register the first id sync during abnormal play (such as reset, search or jump) is an inserted id sync, so you shouldn't use it as an id interrupt. ? dsint: dsi interrupt request in the dvd decoder, out of the 2048 main data, if the system header start_code (00, 00, 01, bb) starts at the 15th byte, and the packet_header (00, 00, 01, bf, **, **) starts at the 39th byte and sub_stream_id (00), the sector is determined to be a dsi pack and sets dsint to 1. when clrint bit is 1, it is cleared to ?0? when micom reads the bit of the register. - don't care in cd mode. ? tosint: top of sector interrupt request request that marks the beginning of the sector during data transfer. cleared to '0' when clrint = ?1? and micom reads the bit of the register. ? trscmplt: interrupt request sent when transfer is completed for the predetermined number of bytes. ? eccmplt: ecc complete interrupt request. interrupt request sent when error correction is completed. cleared to ?0? when clrint = ?1? and micom reads the bit of the register. intstat1: interrupt status register 1 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 4a dvdsint dsint tosint trscmplt eccmplt empty over under reset value 0 0 0 0 0 0 0 0 dt0 dt1 dt2 dt 14 - dt - 17 dt - 38 dt - 44 dt 45 dt 2047 dt0 dt1 ........ dsi section 2048 main data within 1 sector
dvdp data processor ic KS1453 45 steps empty, over, under are the same as those of dvd sync ? empty: when there aren't any data (sector) to be transferred to memory. ? over: memory overflow flag. if the section filled with memory when dvd sync is being generated is above the ots (over threshold size) value, the z-decoder sends the over interrupt. it is cleared to ?0? when clrint = ?1? and micom reads the bit of the register. ? under: memory underflow flag when the section filled with memory is under the uts (under threshold size) value, the z-decoder sends the under interrupt.it is cleared to ?0? when clrint = ?1? and micom reads the bit of the register. - over, under interrupt the new over interrupt only occurs if there is an over after an over interrupt and under interrupt have already occurred. likewise, a new under interrupt only occurs if there is an under after an under interrupt has already occurred. under over under no under under over
KS1453 dvdp data processor ic 46 ? sbqint: subcode q sync interrupt detects subcode sync s0, s1 and generates an interrupt. ? mcpint: micom block copy complete interrupt. various error status information can be found using the interrupt status register. ? eiderr: you can see if there are any errors in the id address data in the efm demodulated data sector being input into the current buffer according to the dvdsint (dvd id sync interrupt) state. 1: errors detected (id ecc error) 0: no errors ? dsierr: you can see if there are any errors in the currently generated dsint ($4a) according to the ? dvdsint (dvd id sync interrupt) state 1: error possible (edc error) 0: no errors ? idconerr: continuity error presence in sector id address of efm data being writed into the buffer (checks the continuity of two consecutive id numbers) 1: discontinuous 0: continuous ? eccerr: error presence in current error corrected data, shown by eccmplt (ecc complete interrupt) state. 1: error present (1 block's ecc results) 0: no errors ? edcflg: error presence in 2064 bytes of sector data output to the a/v decoder, shown by tosint (top of sector interrupt) state. 1: error present 0: no errors ? sbqerr: error presence in subcode data output to the a/v decoder, shown by sbqint (subcode q interrupt) state. 1: error present 0: no errors intstat2: interrupt status register 2 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 4b sbqint mcpint - - - - - - reset value 0 0 - - - - - - errstat: error status register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 4c eiderr dsierr idconerr - eccerr edcflg - sbqerr reset value 0 0 0 - 0 0 - 0
dvdp data processor ic KS1453 47 the sync status of the sector with the interrupt can be found by the intstat1 register ($4a)'s dvdsint interrupt. ? syok: ?1? is read when id sync is detected in the same timing as the inserted timing. ? nosy: ?1? is read when id sync is not detected within window. ? ilsy: ?1? is read when id sync is detected outside window. ? lock: ?1? when the spindle servo is locked. ? gfs: ?1? when the 16-8 frame sync (17.58khz) from playback is found by accurate timing. cd-da subcode q data storage. when s0s1 (serve code block sync) is low, this data is valid. dvdstatus: dvd decoder status register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 4d - - - - syok nosy ilsy - reset value - - - - 0 0 0 - dvdsvstat: dvd decoder servo status register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 4e - lock gfs - - - - - reset value - 0/x 0/x - - - - - cdsubq: cd-da subcode q register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 50 sbq79 - sbq72 59 sbq07 - sbq00 reset value x x x x x x x x
KS1453 dvdp data processor ic 48 this data is used for the id address of the data being currently efm demodulated, seamless buffering control, and disc search. it is valid until next dvdsint interrupt. seekidadr: id data during efm demodulation address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 60 sid31 - sid24 61 sid23 - sid16 62 sid15 - sid08 63 sid07 - sid00 reset value x x x x x x x x n's demodulated data n+1's demodulated data n+2's demodulated data n-1's id output n's id output n+1's id output n-1's id error output n's id error output n+1's id error output idsyz demodulated data sid (7:0) eiderro
dvdp data processor ic KS1453 49 id address of the data being output to the a/v decoder or rom decoder after decoding. this data is valid until the next tosint interrupt. transidadr: id data during data transfers to a/v decoder address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 64 tid31 - tid24 65 tid23 - tid16 66 tid15 - tid08 67 tid07 - tid00 reset value x x x x x x x x address n's sector edc result output dsifg ($4a) & store dsiid address ($90 ~ 93) n+1's edcerr ($4c) operation n's edcerr ($4c) operation internal detection (dsifg) n's data descramble n+1's data descramble x x zirqzd (pin) dvdsint ($4a) dsifg ($4a) dsierr ($4c) (edc result)
KS1453 dvdp data processor ic 50 read access buffer read address setting 70's register address doesn't automatically increase, so it must always be set by micom. radr, rdata: mdab register for direct access on dram (mdab = 1) (read/write register) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 70 - - - adr20 adr19 adr18 adr17 adr16 71 adr15 adr14 adr13 adr12 adr11 adr10 adr9 adr8 72 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 rdata: data read from buffer (when mdab = 1) 73 rdt7 rdt6 rdt5 rdt4 rdt3 rdt2 rdt1 rdt0 reset value all zero zcs mrza mwr mrd mdat (7:0) $70 radrh radrm register adr. $70 select adr20 ~ adr16 value stored in $70 - register pointer automatically changed to $71. - adr15 ~ adr8 value stored in $71 register.
dvdp data processor ic KS1453 51 buffer reading zcs mrza mwr mrd mdat (7:0) zwait $73 rdata1 rdata2 register adr. $73 select. - store the buffer data selected by radr ($70~$72)'s buffer pointer into the register $73 (rdata1: rdt7~rdt0). - enable zwait (low) after mrd falling, and when rdata1 storage in register $73 is completed, disable zwait signal. - when zwait signal is disabled (high), micom read rdata1 and mrd rising. - if micom read rdata1, the $73 register pointer stays the same, while the rdat ($70~72)'s buffer pointer automatically increases to move rdata2 to register $73. - enable zwait (low) after mrd falling, then disable zwait when rdata2 is completely stored in register $73. - when zwait signal is disabled (high), read rdara1 and mrd rising after rdata2 read. x x
KS1453 dvdp data processor ic 52 last read out address reading read the value 'buffer pointer+1' from the last read out. zcs mrza mwr mrd mdat (7:0) $70 radrm radrh register adr. $70 select read register $70's value - register pointer automatic change to $71 - read register $71's value
dvdp data processor ic KS1453 53 sector unit number of the current buffer after efm data write completion. valid until the next dvdsint interrupt. 1 sector carried out while wrst low is stored. when wrst ? 'l', the completed sector no.value is output (valid from first dvdsint after wrst low). sector unit number of the current buffer after error correction is completed. valid until the next eccmpt interrupt. when eccst ? 'l', immediately stopped. when eccst ? 'l', (ecc completed < or ended > block no.) is read. buffer unit number of the data continuing to be output to the a/v decoder or rom decoder after the decoding. valid until the next tosint interrupt. when trst ? 'l' outputs the transfer completed unit number. unit number of the buffer that stores the dsi sector after dsifg ($4a) generation. valid until the next dvdsint interrupt. buffering end sector unit number address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 80 b9 - b8 81 b7 - b0 reset value b (9:0) = 3ff ecc end sector unit number address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 82 b9 - b8 83 b7 - b0 reset value b (9:0) = 3ff transfering end sector unit number address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 84 b9 - b8 85 b7 - b0 reset value b (9:0) = 1ff dsi unit number address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 86 b9 - b8 87 b7 - b0 reset value b (9:0) = 000
KS1453 dvdp data processor ic 54 buffer write during re-search or jump control - set wrst out of write to ?0?, reassign the memory address to wba, and write. wba wba + x xxx sid sid + 1 sid sid + x sid + x + 1 wba + x xxx sid + 1 wba sid + 2 wba + 1 wba + 2 sid + x dvdsint ($4a) wrst ($12) rwa ($80, $81) wba ($30, $31) seekidadr ($60-$63) actua id of the data being stored ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
dvdp data processor ic KS1453 55 write control according to over or under interrupt - stopping and starting write is accomplished by controlling wrst. the write location isn't reloaded. wba xxx sid sid + 1 sid sid + 3 sid + 4 wba + 3 xxx sid + 1 wba sid + 2 wba + 1 wba + 2 sid + 3 dvdsint ($4a) wrst ($12) rwa ($80, $81) wba ($30, $31) seekidadr ($60-$63) actua id of the data being stored ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ wba
KS1453 dvdp data processor ic 56 ecc control - if eccst is ?0? while must be carrying out ecc, always must be set the next ecc address to wea. - if eccst is ?0?, stop the current ecc operation in execution. wea xxx cid cid + 16 cid cid + n + 16 sid + n + 32 wea + n + 16 xxx cid + 16 wea cid + 32 wea + 16 eccmplt ($4a) eccst ($12) rea ($82, $83) wea ($32, $31) eeida ($94-$97) id of data being corrected ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ wea + n xxx cid + n wea + n xxx cid + n cid + n + 16 ~ ~ eccerr ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ dvdsint ($4a)
dvdp data processor ic KS1453 57 control during transfer transfer after reassigning the memory address during transferring: - set trst to ?0?, reassign a new address to wta, and start re-transferring by setting trst to ?1?. (even if trst is ?0?, reassignment must come after transferring the specified sector amount.) wta tid tid + 1 tid + 2 tid tid + x +1 tid + x +1 wta + x xxx tid + 1 wta tid + 2 wta + 1 wta + 2 tid + x tosint ($4a) trst ($12) rta ($84, $85) wta ($34, $35) transidadr ($64-$67) actua id of data being transferred ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ wta + x tid + x xxx transfer complete even when trst = 0
KS1453 dvdp data processor ic 58 stopping and starting transfer by controlling only trst wta tid tid + 1 tid + 2 tid tid + 4 tid + 4 wta + 3 xxx tid + 1 wta tid + 2 wta + 1 wta + 2 tid + 3 tosint ($4a) trst ($12) rta ($84, $85) wta ($34, $35) transidadr ($64-$67) actua id of data being transferred ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ wta tid + 3
dvdp data processor ic KS1453 59 sector unit number of the completely descrambled buffer the id address corresponding to the end sector unit number of the buffer that has just finished error correction. this data is valid until the next eccmpt interrupt. dsi sector's id address stored in the buffer after dsifg ($4a) generation. this data is valid until the next dvdsint interrupt. the difference between the sector unit number of a descrambled buffer and the unit number after transfer to the a/ v decoder or rom decoder. you can find out how much extra data you have to transfer. descramble end sector unit number address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 88 b9 - b8 89 b7 - b0 reset value b (9:0) = 3ff ecc end id address address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 94 b31 - b24 95 b23 - b16 96 b15 - b8 97 b7 - b0 reset value x x x x x x x x dsi id address address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 9c b31 - b24 9d b23 - b16 9e b15 - b8 9f b7 - b0 reset value x x x x x x x x remaining data size (sector unit) address bit7 bit bit5 bit4 bit3 bit2 bit1 bit0 f0 b9 - b8 f1 b7 - b0 reset value x x x x x x x x
KS1453 dvdp data processor ic 60 over, under interrupt ($4a) application renew transfer address continuetransfer after renewing address assign buffer address store buffer stop storing buffer over under wrst rwa wba dvdsint trst rta wta tosint
dvdp data processor ic KS1453 61 5 interface micom i/f micom i/f timing read cycle write cycle address data zcs mrza mwr mrd mdat (7:0) address data zcs mrza mwr mrd mdat (7:0)
KS1453 dvdp data processor ic 62 read cycle timing write cycle timing mrza zcs mwr mrd mdat [7:0] t mrza-hold t zcs-setup t zcs-hold t mrza-setup t mwr-inactive t mrd-inactive t mrd-active t read-valid t h1 t h2 t rdat-hold mrza zcs mrd mwr mdat [7:0] t mrza-hold t zcs-setup t zcs-hold t mrza-setup t mrd-inactive t mwr-inactive t mwr-active t wdat-setup t wdat-hold valid
dvdp data processor ic KS1453 63 there should be no glitches in signals mrza, zcs, mwr, and mrd. time description min max unit t mrza-setup mrza setup 0 ns t mrza-hold mrza hold 10 ns t zcs-setup zcs setup 10 ns t zcs-hold zcs hold 10 ns t mwr-inactive mwr inactive 30 ns t mwr-active mwr active pulse width 30 ns t mrd-inactive mrd inactive 30 ns t mrd-active mrd active pulse width 120 ns t read-valid mrd active to read data valid 60 ns t h1 mrd active to mdat(7:0) ow-impedance - ns t h2 mrd inactive to mdat(7:0) igh-impedance - - ns t rdat-hold read data hold after mrd inactive 10 ns t wdat-setup write data setup 20 ns t wdat-hold write data hold 10 ns
KS1453 dvdp data processor ic 64 av decoder i/f equal spacing timing transfer method (dvd-p i/f) mode1: 2048 bytes main data only ? compared to mode2, tdata-access has a delay longer by 16bytes at the beginning of data transfer, but the overall data rate is the same. mode2: 2064 bytes data in a sector (4bytes id + 2bytes iec + 6bytes rsv + 2048bytes main data + 4bytes edc) ? the dter signal is output in units of sectors. ? data is taken at cstrobe/dataclk's falling edge (rising edge in reverse mode). ? cstrobe/dataclk's duty cycle is not regular ? tcspulse-high/low: 4t ? tcspulse-cycle: 8t (240 ns) ? cstrobe, datreq, datack's edge is programmable (reversible). cstrobe/ dataclk tos t w-tos t cspulse-high t cspulse-low t cspulse-cyclk t data-hold-str t data-setup-str t data-access t ack-setup invalid ack-hold sdata (7:0) datreq datack dter
dvdp data processor ic KS1453 65 timing spec time description min max unit t data-setup-str sdata(7:0) setup to cstrobe asserted (synchronous) 5 4t ns t data-hold-str sdata(7:0) hold from cstrobe asserted (synchronous) 5 4t ns t d delay from datreq asserted to datack (asynchronous) 0 ns t ack-low datack low time (asynchronous) 50 ns t cspulse-cycle datack period 236 ns t ack-hold datack disabled time 12 4t ns t sdata-d sdata(7:0) delay from datack falling 10 ns t ack-setup datack setup to cstrobe (synchronous) 5 ns t ack-hold datack hold from cstrobe (synchronous) 5 ns
KS1453 dvdp data processor ic 66 cd-da/ cd-rom/ v-cd data output timing (format 1, format 2) bclk 15 14 13 12 11 10 3 2 1 0 14 13 12 11 10 15 for upper byte (h = error) for lower byte (h = error) for upper byte (h = error) r_ch error l_ch error left cannel invalid invalid right cannel lrck cdata c2po (rom, v-cd) c2po (cd- da) 9 8 7 6 5 4 9 8 7 6 5 bclk for upper byte (h = error) for lower byte (h = error) for upper byte (h = error) r_ch error l_ch error left cannel invalid invalid right cannel lrck cdata c2po (rom, v-cd) c2po (cd- da) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0 f o r m a t 2
dvdp data processor ic KS1453 67 subcode output i/f (for cd-g) i: after wfsy becomes falling edge, sqck becomes ?l? at about 10 m sec. ii: if s0s1 is ?l?, subcode p is output, and if ?h?, subcode sync s0 and s1 are output. iii: if pulses are input to the sqck terminal over seven, subcode data (p, q, r, s, t, u, v, w) are repeated. 1 subcode sync = 98 efm frames (1 efm frame = 7.35khz, 1 subcode sync = 75hz) 98 efm frames = 2bytes for subcode sync (s0, s1) + 96bytes for subcode data 96bytes subcode data = 1(p) bit 96 + 1(q) bit 80 + 16bits (crc for edc) for cdp + 6(r - w) bits 96 for cdg 1 2 3 4 5 6 7 8 ii q r s t u v w iii i sos1 wfsy sqck sqdt 1 0 2 3 4 5 6 95 96 97 ~ ~ p q r s t v w sos1 wfsy sqck sqdt u
KS1453 dvdp data processor ic 68 sqdt read should be completed when wfsy is low (t wfsylw ). time description min typ max unit t d delay time from wfsy low to sqck high edge for "p" subcode bit (sqck input) 1 - - us t sqckhw sqck (input) high pulse width 1 - 3 us t sqcklw sqck (input) low pulse width 1 - 3 us t hold sqdt hold time from sqck high 0 - - ns t s0s1hw s0s1 high pulse width - 136 - us t bp block period - 13 - ms t fp frame period - 136 - us t wfsylw wfsy low pulse width - 68 - us t d wfsy sqck sqdt s0s1 wfsy sqck t fp t wfsylm t s0s1hw t bp p q r t hold t sqckhw t sqcklw byte 0 byte 1 byte 2 byte 3 byte 4 byte 97 byte 0 byte 1
dvdp data processor ic KS1453 69 6 miscellaneous external dram memory map ecc 13 block can be stored using 4m dram, and can carry out the following: efm+demodulation 1 block, ecc 1 block, descramble 1 block, and trans 1 block. : memory mapping (512 x 512 x 16) for dvdp. 1 sector standard: id(4), iec(2), rsv(6), dpdata(2048), edc(4), pi(120), po(182) memory mapping definition by sector pi: 128byte per sector. - 1 row address increases per 8 sectors. po: 256byte per sector. - 1 row address increases per 4 sectors. id, iec, rsv, edc: 32bytes per sector. - 1 row address increases per 32 sectors. figure 7. external dram memory map dpdata (208 x 2048 byte) 13 ecc block -> 208 sector pi (208 x 120 byte) po (208 x 182 byte) un - used id + iec + rsv + edc (208 x 16 byte) 1 1001 1111 (415) 1 1011 1001 (441) 1 1110 0011 (499) 1 1111 0111 (503) 1 1111 1111 (511) 1 1111 1000 (504) 1 1111 0100 (500) 1 1100 0000 (448) 1 1010 0000 (416) 0 0000 0000 (0)
KS1453 dvdp data processor ic 70 address mapping data mapping pi mapping ecc block number id sector number row address column address 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x 1 0 0 0 0 0 0 0 1 x x x x x x x x x x . . . . . . . . . 15 0 0 0 0 1 1 1 1 x x x x x x x x x x 1 0 - 15 0 0 0 1 x x x x x x x x x x x x x x 2 0 - 15 0 0 1 0 x x x x x x x x x x x x x x . . . . . . . . . . . . 12 0 1 1 0 0 0 0 0 0 x x x x x x x x x x . . . . . . . . . 15 1 1 0 0 1 1 1 1 x x x x x x x x x x ecc block number id sector number row address column address 0 0 1 1 0 1 0 0 0 0 0 0 0 0 x x x x x x 1 1 1 0 1 0 0 0 0 0 0 0 1 x x x x x x . . . . . . . . . 15 1 1 0 1 0 0 0 0 1 1 1 1 x x x x x x 1 0 - 15 1 1 0 1 0 0 0 1 x x x x x x x x x x 2 0 - 15 1 1 0 1 0 0 1 0 x x x x x x x x x x . . . . . . . . . . . . 12 0 1 1 0 1 1 1 0 0 0 0 0 0 x x x x x x . . . . . . . . . 15 1 1 0 1 1 1 0 0 1 1 1 1 x x x x x x
dvdp data processor ic KS1453 71 po mapping id(4) + iec(2) + rsv(6) + edc(4) lower 4bits is mapped by sectors ? id: ?0000? - ?0001?, iec: ?0010?, rsv: ?0011? - ?0110?, edc: ?1000? - ?1001? ecc block number id sector number row address column address 0 0 1 1 1 0 0 0 0 0 0 0 0 x x x x x x x 1 1 1 1 0 0 0 0 0 0 0 1 x x x x x x x . . . . . . . . . 15 1 1 1 0 0 0 0 1 1 1 1 x x x x x x x 1 0 - 15 1 1 1 0 0 0 1 x x x x x x x x x x x 2 0 - 15 1 1 1 0 0 1 0 x x x x x x x x x x x . . . . . . . . . . . . 12 0 1 1 1 1 1 0 0 0 0 0 0 x x x x x x x . . . . . . . . . 15 1 1 1 1 1 0 0 1 1 1 1 x x x x x x x ecc block number id sector number row address column address 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 x x x x 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 x x x x . . . . . . . . . 15 1 1 1 1 1 1 0 0 0 0 1 1 1 1 x x x x 1 0 - 15 1 1 1 1 1 1 0 0 0 1 x x x x x x x x 2 0 - 15 1 1 1 1 1 1 0 0 1 0 x x x x x x x x . . . . . . . . . . . . 12 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 x x x x . . . . . . . . . 15 1 1 1 1 1 1 1 1 0 0 1 1 1 1 x x x x
KS1453 dvdp data processor ic 72 circuit application figure 8. circuit application rf (ks1461) servo (ks1452) KS1453 mpeg decoder cdg 4m bit dram micom p17 -p20, p22-p25, p27-p30, p32-35: dd[15:0]_out/ p45-p46, p48- p54: dadr[8:0]_out/ p39, p40: zwe[1:0]_out/ p41, p43: zoe[1:0]_out/ p37: zlcas_out/ p38: zucas_out/ p44: zras_out p73-p76, p78-p81: pwmo[7:0]_out p104: plck_in p114: fg_in p116: efmi_in p106: plllock_out p107: clvlock_out p108: serlock_out p109: mdp_out p110: mds_out p113: mon_out p115: fsw_out p5-p12: mdat[7:0]_bi/ p124: zrst_in p2: zcs_in/ p3: mrza_in p125: zwait_out/ p126: zirqzd_out p127: mrd_in/ p128: mwr_in p98: test0_in p99: test1_in p100: test2_in p122: test3_in p60: cdata p61: lrck p62: blck p63: c2po p64: sqdt p65: wfsy p66: sos1 p67: sqck (cd mode) p60- p66: sdata[0:6]_out p67: sdata[7]_bi (dvd mode) p57: tos_out p58: datack_out p69: cstrobe_out p70: datreq_in p71: dter_out
dvdp data processor ic KS1453 73 package dimensions figure 9. package dimensions 128-qfp-1420 #128 20.00 0.20 22.00 0.30 14.00 0.20 16.00 0.30 0.15 + 0.10 - 0.05 0-8 0.10 max #1 (0.75) 0.50 0.20 0.05 min 2.10 0.10 2.40 max 0.50 0.20 + 0.10 - 0.05

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